ChipScope™ Family
Statistical Design Optimization

ChipScope™ offers low power optimization method to the designs analyzed using ChronoVA™/SSTA.

Voltage Constraint Map Generation
ChipScope™/VC

The first product of ChipScope™ Family, VC (Voltage Constraint Map Generation) is introduced in the latest product release 2007.3.


Features of ChipScope™/VC is as listed below:

  • Based on the variation range of parameters such as global process variation and Vdd, ChipScope™/VC analyzes the minimum supply voltage to maintain the proper timing performance and generates the map.
  • High speed delay evaluation with multiple conditions using parallel processing.

ChipScope™/VC allows you to easily apply the supply voltage scaling to reduce dynamic power consumption of the design.

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Statistical design solutions -
Product Line-Up
ChronoVA™ Family
   ChronoVA™/LC
   ChronoVA™/LVA
   ChronoVA™/SSTA
   ChronoVA™/CA
   ChronoVA™/PA
   ChipScope™ Family
      ChipScope™/VC