ChronoVA™ User Experience

Fujitsu ASIC/COT Design

By courtesy of Fujitsu Ltd., its ASIC and COT design flow using ChronoVA™ is introduced here. At Fujitsu, SSTA is used for those paths which do not close timing using ordinary STA, to eliminate pessimism of the traditional corner case sign-off. ChronoVA™/SSTA reads the timing list generated by the STA tool, and apply statistical analysis on those paths.

Fujits explains the flow and the benefit of SSTA as below to its ASIC and COT customers:

• ChronoVA™/LVA adjusts the physical variation depending on the cell layout;
• ChronoVA™/LVA allows to generate accurate SSTA timing library through Monte Carlo analysis using the adjusted variation;
• User can use ChronoVA™/SSTA to analyze the paths statistically and obtain the distribution of delay or slack of the paths;
• The result reflects the variation of cell characteristics, input slew and output load as well as multi-stage effect, and is better correlated with the actual device characteristics to reduce pessimism of the traditional corner case model.

Design Example

One example using 65nm design of 1.5 million instances is shown comparing with traditional STA result.

	STA	SSTA	Comparison	Conditions
Worst Slack	-660ps	-394ps	Improved by 266ps	Target frequency: 294MHz Clock period: 3,400ps
Operating frequency	246MHz	264MHz	Improved by 6.82%
CPU time	1,611 sec	1,822 sec	A little (13.1%) longer	Evaluated 11 thousand paths Using Opteron 64bit, 2.4GHz machine with RHEL 3.0
Memory usage	8,124MB	7,937MB	Almost comparable (97.7%)

As one more example, final distribution of the slack on another design is shown below:

Fujits offers ChronoVA™/SSTA timing libraries of 90nm and 65nm technology to its customers who design chips with Fujitsu. Anova also offers special license of ChronoVA™/SSTA to those customers. Please contact us for more details.

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