ChronoVA™ Family
Statistical Timing Analysis

ChronoVA™ Software Configuration

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ChronoVA™ family statistical tools are designed to analyze and optimize timing and power of LSI considering process variation. It consists of Unified Variation Database, LC (Library Characterization), SSTA (Statistical Static Timing Analysis), CA (Circuit Analysis using Stochastic Analysis Process) and LVA (Layout Variation Analysis). In addition, ChronoVA™/PA (Path Analysis) tool is available for transistor level Monte Carlo analysis to large circuits such as the critical paths based on the standard cells characterized by ChronoVA™/LC.

Anova Suite™ MDC (Measurement Data Calibration) is another software tool package used to analyze the measurement data. select the most sensitive parameters and calibrate the SPICE model parameters to fit in the original measurement consistently. Process measurement data varies a lot by the company and thus the calibration technique like data mining is not common even with the same tools. So Anova offers Data Calibration Service for foundry or IDM companies.

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Product Line-up

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Anova's statistical design solutions offer the products in the table below. Click the product name for more details.

Product		Function
Statistical data calibration	Anova Suite™	Analysis of process measurement data and modeling of device characteristics
Statistical timing analysis ChronoVA™ Family	ChronoVA™/LVA (Layout Variation Analysis)	Systematic variation effect
	ChronoVA™/LC (Library Characterization)	Library characterization for SSTA
	ChronoVA™/CA (Variation-Aware Circuit Analysis)	SPICE based statistical circuit analysis
	ChronoVA™/SSTA (Statistic Static Timing Analysis)	Statistical static timing analysis
	ChronoVA™/PA (Variation-Aware Path Analysis)	SPICE based statistical path timing analysis

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System Level Timing Path Analysis

ChronoVA™/SSTA, ChronoVA™/CA and ChronoVA™/PA can be hierarchically connected and reusing the lower hierarchy verification result, it is easy to extend the scope of the timing analysis up to system level. You can include transmission line, package or board characteristics describing in the SPICE netlist and assign variation. As an example, loop back testing of SPI4.2 high-speed serial interface is shown below.

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