Statistical Static Timing Analysis
ChronoVA™/SSTA
ChronoVA™/SSTA is a statistical static timing analysis (SSTA) tool.
Two different application modes are offered. One is to get a list of critical
paths from the traditional STA and apply statistical analysis on those
limited number of paths. This mode is called as CPA, Critical Path Analysis.
The other is to use ChronoVA™/SSTA instead of the traditional STA
for full chip analysis. This mode is called as FCA, Full Chip Analysis.
ChronoVA™/SSTA-CPA reads a path list generated by other STA tools,
and analyzes statistically only those paths. This method respects the traditional
corner based timing sign-off and provides relief for timing violations
for some of the paths difficult to close, showing the probability of meeting
the timing.
On the other hand, ChronoVA™/SSTA-FCA is intended for replacing the
traditional STA in the design flow, evaluating the timing of all the paths.
Like other STA tools, ChronoVA™/SSTA-FCA traces all the paths in
the chip, evaluates the race of the clock and the data, and shows the slack
of them statistically. User interface is compatible with the other STA
tools. As an example, timing constraints described in SCF (Standard Constraint
File) and command scripts for other STA tools may be directly applied to
ChronoVA™/SSTA.
Features of ChronoVA?/SSTA are as listed below.
- Built-in native STA engine
- Current SDC support
- Compatible results with standard STA tools
- SI incremental SDF annotation
- Delay calculation support current source models such as ECSM and CCS
- Process On-Chip-Variation
- Proprietary fast and accurate variation model using SAP (Stochastic Analysis
Process)
- Model description in liberty extension format
- Flexible derating factors
- Plug-in with current STA flow
- Industry standard input formats: Verilog, SPEF, SDF, SDC
- TCL interface
- Critical paths filtering using STA timing report
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User Experience
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ChronoVA™ Family