Statistical Static Timing Analysis
ChronoVA™/SSTA
ChronoVA™/SSTA is a high performance statistical static timing analysis (SSTA) tool. Itis fully compatible with today's industry standard STA products, with its uniqe statistical analysis algorighm, ChronoVA™/SSTA can provide full chip SSTA with equivelent or even better performance then other STA solutions.
ChronoVA™/SSTA can read timing report file generated by other STA tools,
and analyzes statistically only the nets shown on the report.
This method respects the traditional corner based timing sign-off and
provides relief for timing violations for some of the paths difficult to close,
showing the probability of meeting the timing.
ChronoVA™/SSTA plugs into today's STA flow, it applies statistical static timing analysis
on the whole design. User interface is compatible with the other STA
tools. As an example, timing constraints described in SDC (Standard Design Constraint)
and command scripts for other STA tools may be directly applied to ChronoVA™/SSTA.
Features of ChronoVA?/SSTA are as listed below.
- Built-in native STA engine
- Current SDC support
- Compatible results with standard STA tools
- SDF and SI incremental SDF annotation
- Delay calculation support current source models such as ECSM and CCS
- SI Delay calculation support current source models such as ECSM and CCS
- Process On-Chip-Variation
- Proprietary fast and accurate variation model using SAP (Stochastic Analysis
Process)
- Model description in liberty extension format
- Support Multi-voltage design by CPF
- Support IR Drop impact on timing
- Flexible derating factors
- Plug-in with current STA flow
- Industry standard input formats: Verilog, SPEF, SDF, SDC
- TCL interface
- Multithread, multiprocess for speed enhancement
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User Experience
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ChronoVA™ Family