Total Solution for Variation-Aware Design
Statistical design tools such as SSTA (Statistical Static Timing Analysis),
sensitivity analysis of circuit characteristics over variation, etc. are
now offered from many EDA vendors. Most of them, however, are just a point
solution, and believed ineffective if they merely target to reduce guardband.
Anova Solutions provide complex SoC development team with a total solution
for design for yield thanks to SAP, Anova's core technology for variation
aware design, which enables the user to deal with the impact of process
variation at any step of the design implementation flow.
This total solution brings you with the following features and benefit.
- Statistical analysis and optimization capability easily added on the existing
design flow without any modification;
- Common unified variation model from device level to full chip level;
- Most appropriate verification method for logic and analog circuit, respectively;
- Verification of complex timing path not only mixed logic and analog circuit
but also including package, board and transmission lines by simply adding
the characteristics;
- Leakage power evaluation as well as timing;
- Optimization for both high performance yield and low power concurrently
taking global process variation and operation environment;
Anova also provides you with service contract for data analysis and library characterization, and consultation
based on your data.
Using Anova Tools
As the summary, here are some of the practical applications of Anova statistical
design environment. Anova allows you to:
- evaluate the design over process variation and layout dependency.
- estimate the characteristics and yield with Vth or gate length shift.
- make the design more robust through What-if analysis thanks to the high-speed
Monte Carlo like simulation.
- adopt global process variation.
- estimate the characteristics and yield with deterioration of the process,
and obtain optimal target process conditions or traditional sign-off corner
conditions.
- estimate the characteristics and yield when the design is transferred to
different manufacturing site.
- retarget the library without SPICE simulation run when process condition
is changed.
- generate timing (STA) libraries for traditional multiple corner conditions.
- obtain optimal manufacturing or operating conditions to meet both high
performance and low power requirements.
- derive optimal Vth for manufacturing target.
- derive minimum supply voltage to achieve target performance.
Operating Environment
Operating Systems supported
Redhat Enterprise Linux 3 (RHEL3) and its updates
Redhat Enterprise Linux 4 (RHEL4) and its updates
Redhat Enterprise Linux 5 (RHEL5)
This applies to license server as well.
Platforms
X86 Intel and AMD 32bit architecture
X86_64 Intel-EMT64 and AMD-AMD64 architecture except Intel-Itanium (IA64)
architecture
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